Parallel Multipler
The PMU accepts two serial inputs as multiplicand and multiplier in one word time, produces their properly rounded product by means of a parallel algorithm in one more word time, and shifts the product out in the next word time while inputs for the next operation are simultaneously shifted in. The parallel multiply algorithm used is called Booth’s Algorithm (1). Two’s complement representation is used for negative numbers. The PMU consists of three registers, the Multiplicand (M), the Multiplier (R), and the Product (P). The 20-bit parallel multiply is accomplished in one word time of 106.6 microseconds.
(1) CHU, YOAHAN, “Digital Computer Design Fundamentals,” 1962, Mc Graw Hill, Inc., page 32
Parallel Divider
The PDU accepts two serial inputs as divisor and dividend in one word time, produces a truncated quotient by means of a parallel algorithm in one more word time, and shifts the product out in the next word time while inputs for the next operation are simultaneously shifted in. The parallel divider algorithm used is called Non-Restoring division (1). Two’s complement representation is used for negative numbers. The PDU consists of three registers, the Divisor (Z), the Dividend (D), and the Quotient (Q). The 20-bit parallel divide is accomplished in one word time of 106.6 microseconds.
(1) CHU, YOAHAN, “Digital Computer Design Fundamentals,” 1962, Mc Graw Hill, Inc., page 39
CPU
The CPU performs logical and arithmetic operations and generates specific data and logic outputs. The CPU accepts an instruction command of 4 bits. This command specifies details of the operation. The fundamental logical operation of the CPU is the limit function. The SLF consists of three registers, Upper (U), Parameter (P), and Lower (L). One of these registers is picked as the output, Q, at the end of the word. Register L is picked if P < L (algebraically), register U is picked if P >U and not = P >=L (algebraically). Other logical functions, such as, logical products, Gray code conversions, forced 1’s, forced 0’s, and two’s complements operations are performed. The 20-bit logical operations are accomplished in one word time of 106.6 microseconds.
Random Access Memory
The RAM operates as a random access read-write memory of sixteen registers of 20-bits each. Information is shifted serially into and out of selected registers during a word time. the RAM accepts a five bit instruction command to control its operation. Four bits select one of sixteen registers and one bit controls the read or read/write mode of the selected register. The one output from the RAM is the contents of the selected register.
Steering Logic Unit
The SLU operates as a three-channel serial digital data multiplexer. Information is shifted serially through the SLU during one word time. A 15-bit instruction command specifies which input or input combinations are to be “steered” to each of three data outputs. Inputs to the SLU may come from external digital sources (sensors, analog-to-digital converters), PDU, PMU, RAM, ROM. The output of the SLU typically goes to the PDU, PMU or RAM.
Read-Only Memory
The ROM operates as a 2560-bit random access/sequential access fixed memory. The ROM internally stores fixed patterns of 128 words of 20 bit length for serial output. The patterns are specified by the user as command instructions for operating the PDU, PMU, SLU, CPU, and RAM. The ROM has provision to accept a 20-bit serial binary word address. The first seven bits indicates which of the 128 words are to be accessed, and the nest three bits specifies, by manufacture mask decoding, which ROM out of a possible eight ROM group should have its output enabled.
The address management is accomplished by a register counter contained within the ROM. This counter has the following capability: (1) resettable, (2) steppable such that the memory can be sequenced through the 128-bit word field, (3) accepts a retain address command and holds the present address, and (4) accepts a numerical input for independent address modifying or loading. To accomplish this address management, six logic inputs (reset, retain, increment, load, add, subtract) and one address data input are provided.
The ROM has two outputs, data output and parity error output. The data output contains the 20-bit serial data word addressed by the address register. The parity error output is from a device that changes state for every occurrence of state changes in the enabled data output.
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