The ROM operates as a 2560-bit random access/sequential access fixed memory. The ROM internally stores fixed patterns of 128 words of 20 bit length for serial output. The patterns are specified by the user as command instructions for operating the PDU, PMU, SLU, CPU, and RAM. The ROM has provision to accept a 20-bit serial binary word address. The first seven bits indicates which of the 128 words are to be accessed, and the nest three bits specifies, by manufacture mask decoding, which ROM out of a possible eight ROM group should have its output enabled.
The address management is accomplished by a register counter contained within the ROM. This counter has the following capability: (1) resettable, (2) steppable such that the memory can be sequenced through the 128-bit word field, (3) accepts a retain address command and holds the present address, and (4) accepts a numerical input for independent address modifying or loading. To accomplish this address management, six logic inputs (reset, retain, increment, load, add, subtract) and one address data input are provided.
The ROM has two outputs, data output and parity error output. The data output contains the 20-bit serial data word addressed by the address register. The parity error output is from a device that changes state for every occurrence of state changes in the enabled data output.
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